来源：EETOP

本论文分享论坛资深版主JoyShockley（胡诣哲博士）及课题组的JSSC最新论文第一篇——电荷域小数分频全数字锁相环。

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https://bbs.eetop.cn/thread-988756-1-1.html

这是课题组成立两年以来第一篇JSSC – 电荷域小数分频全数字锁相环。

也是个人第一篇Last Author 文章，希望读者喜欢。

https://ieeexplore.ieee.org/abstract/document/10981601  （开放获取，免费下载）

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论文部分截图：

Abstract:

We propose a charge-domain fractional-N all-digital phase-locked loop (ADPLL) that employs charge-steering sampling (CSS) of a sinusoidal reference waveform. 

The well-known issue of ΔΣ quantization error in fractional-N operation is compensated by a capacitive digital-to-analog converter (CDAC), which serves the conventional role of a digital-to-time converter (DTC). 

This CDAC is further merged with the inherent CDAC of a successive approximation register (SAR) analog-to-digital converter (ADC), which is exclusively used for digitizing the time-error mainly induced by the phase noise (PN). 

Initially, the combined CDACs are preset to VDD, and then discharged during a short digitally controlled oscillator (DCO)-divider-triggered pulse via a pseudo-differential MOS pair directly driven by the input reference sinusoidal waveform. Owing to the gentle slope of the reference waveform, the charge-domain fractional-N operation achieves a wide and linear time-error detection (TD) range. 

Furthermore, by reinterpreting the SAR ADC output using multi-bit midrise encoding, the effective time-to-digital conversion (TDC) gain is boosted by bang–bang (BB) effects while maintaining fast and robust locking. To accurately model the CSS current, we introduce a damped-sine waveform model incorporating harmonics, providing comprehensive insight into the CSS-TD gain, even with short-channel devices. 

Fabricated in 22 nm CMOS, the prototype achieves an rms jitter of 96 fs at 24 GHz with a reference spur of -60 dBc in integer-N mode, while 167.8 fs at approximately 24.5 GHz with a worst in-band spur of -47.8 dBc in fractional-N mode. The occupied area is only 0.08 mm2.

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